3D patterning

For photolithographic patterning of conductive and dielectric layers on 3D MEMS surfaces with incrementally level, sloping and even extremely steep topologies it is necessary to apply the required photoresist as conformly as possible.

To this end, in recent years spray coating of photoresist has become established as a versatile, low cost technique with batch process capability. At CiS this method has been employed and developed further for many years. We have succeeded in increasing conformity considerably so that now higher structural resolutions beyond topologies are possible.

For special applications it may also be worthwhile to use electrochemically precipitative photoresist as an alternative. This is precipitated in an electroplating bath while applying a current very consistently on a conductive surface layer.

In order to be able to expose the consistently precipitated photoresist layers and achieve structural integrity, CiS has acquired a new mask aligner. It boasts definitely improved depth imaging properties compared with conventional devices.




The development of exposed photoresist layers is conducted depending on the selected topology aspect ratios. At low rates submersion or paddle processing can be carried out. At high rates spraying is required, in order to achieve sufficient developer saturation.


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